1. Field of the Invention
This invention relates to a sense amplifier, and more particularly to a sense amplifier which is useful in a CMOS semiconductor integrated circuit used in a one-chip microcomputer, a microprocessor or a memory.
2. Description of the Prior Art
FIG. 3 shows a prior art sense amplifier used in a semiconductor memory device. The sense amplifier of FIG. 3 comprises PMOS precharging transistors 11 and 12, NMOS amplifying transistors 13 and 14, and an NMOS driving transistor 15. A precharge signal PRE (active-low) is supplied to the gates of the precharging transistors 11 and 12. The precharging transistors 11 and 12 are connected to bit lines BIT and BIT which are connected to memory cells (not shown), respectively. Hereinafter, signals appearing on the bit lines BIT and BIT are referred to as "BIT" and "BIT", respectively. To the gate of the driving transistor 15, a sense amplifier drive signal SA is supplied. The timings of the signals PRE and SA are so controlled that they will not become active at the same time.
When the signals BIT, BIT and SA are adequately controlled by an external circuit (not shown), the sense amplifier of FIG. 3 operates according to the operation timing shown in FIG. 4A. The operation of the sense amplifier will be described by illustrating the reading operation in which data is read out from one of the memory cells. First, the precharge signal PRE is set LOW to turn on the transistors 11 and 12, so that both the signals BIT and BIT are HIGH. At this time, the sense amplifier drive signal SA remains LOW, and the amplifying transistors 13 and 14 do not operate. The precharge signal PRE becomes HIGH at time t.sub.11, and the levels of the signals BIT and BIT change depending upon the data read out from the memory cell (in FIG. 4A, the level of the signal BIT becomes lower). Then, the sense amplifier drive signal SA is made HIGH at t.sub.12 to turn on the transistor 15, whereby the amplifying transistors 13 and 14 start the sense amplification of the potential difference between the signals BIT and BIT.
The above-mentioned prior art sense amplifier requires the provision of an external circuit which controls the timings of the signals BIT, BIT and SA. Furthermore, the sense amplifier has a problem in that, when the external circuit fails to adequately control the timings of the signals BIT, BIT and SA, the sense amplifier malfunctions as described below. For example, when the level of the signal SA is erroneously raised at time t.sub.13 (FIG. 4B) while both the signals BIT and BIT remain HIGH, the levels of both the signals BIT and BIT are pulled down. If the potential of the bit line BIT (which should be higher) is pulled down to a lower level than that of the bit line BIT (which should be lower), the potential relationship between the signals BIT and BIT becomes opposite to that they should have, as shown by broken lines in FIG. 4B.